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Job Description
Experience Accountable for innovative DFT implementation(Scan, MBIST, LBIST & Boundary Scan) at the RTL and Gate level for a given SOC at Hard macro and chip top level.
- Generate and validate ATPG patterns using simulations.
- Shall Validate the DFT implementation using RTL and Gate level simulation.
- Work with Multi-functional Teams on STA, Synthesis, LEC, CLP, verification & Validation.
- Must have experience with Siemens, Synopsys and/or Cadence Cad tools.
- Shall have experience in coding with Verilog, VHDL, C/C++, TCL, Perl and or Python
About Surya Systems
Surya Systems, where we redefine success through our comprehensive Staffing, Training, and Consulting Solutions. At the heart of our approach lies nurturing our resources, empowering them with unparalleled learning opportunities, and providing expert mentoring. We are passionate about guiding individuals towards their full potential and unlocking remarkable growth within the industry. Join us on a transformative journey where we invest in your future, cultivating a thriving ecosystem of talent, and together, we will create unparalleled opportunities for success.
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